module Phaser: sig
.. end
type
t
val make : t option -> int32 -> t
val arrive : t -> int32
val arrive_and_await_advance : t -> int32
val arrive_and_deregister : t -> int32
val await_advance : t -> int32 -> int32
val await_advance_interruptibly : t -> int32 -> int32
val await_advance_interruptibly_time : t -> int32 -> int64 -> TimeUnit.t -> int32
val bulk_register : t -> int32 -> int32
val force_termination : t -> unit
val get_arrived_parties : t -> int32
val get_parent : t -> t option
val get_phase : t -> int32
val get_registered_parties : t -> int32
val get_root : t -> t
val get_unarrived_parties : t -> int32
val is_terminated : t -> bool
val register : t -> int32